The present invention relates to a technique which is effective when applied to a semiconductor integrated circuit device (hereafter referred to as an "IC") and, more particularly, to a technique which is effective when applied to a dynamic type random access memory (hereafter referred to as a "DRAM").
The charge stored in the capacitor of the memory cell of the DRAM is subjected to the influences of the minority carriers which are generated in a semiconductor substrate (which will be referred to as a "substrate").
It has been proposed (as is disclosed in Japanese Patent Laid-Open No. 58--63939) that a carrier trapping region for trapping the minority carriers can be formed in the peripheral portion of a memory cell array.
The carrier trapping region is usually formed by the step of forming the source and drain regions of a MISFET. The carrier trapping region is formed to have a depth of about 0.3 to 0.4 microns from the main surface of the substrate by making the source and drain regions shallow.
I, the present inventor, have found out the following problems belonging to the carrier trapping region according to the aforementioned proposal.
The number of the minority carriers to be trapped is reduced by making the carrier trapping region shallow. As a result, the capacitor of the memory cell, which has its capacitance reduced by the high integration, becomes more liable to be influenced by the minority carriers.
On the other hand, another capacitor (which will be called a "trench type capacitor") is constructed (as is disclosed in Japanese Patent Published No. 58--12739) by using a trench or moat (which will be called a "trench"), which extends from the main surface into the inside of the substrate. The aforementioned carrier trapping region cannot trap the minority carriers which are generated in the deep portion of 3 to 5 microns where the trench is present.